rg-asm release notes

The assembler and linker for Atari ST, TT and Falcon. Newest release first.

0.8.8 — 2026-10-09

Mixed-mode assembly documentation, updated tooling branding, and expanded DSP quality assurance coverage.

Improvements

• Mixed-mode assembly documentation: updated user documentation, command-line guides, and reference specifications to formally standardise on mixed-mode assembly terminology for in-file 680x0 and DSP56001 code.
• DSP quality assurance verification: added automated test suites covering DSP56001 arithmetic, parallel move encodings, hardware loop nesting, and mixed-mode wire packaging.

0.8.7 — 2026-10-09

Routing of DSP warnings and diagnostics to error logs and comprehensive CLI acceptance coverage.

Bug fixes

• DSP diagnostics file logging: warnings and errors encountered during DSP assembly are now appended to diagnostic log files specified by --errors, matching the behaviour of host 68k assembly diagnostics.

Improvements

• Command-line interface verification: added test coverage for option combinations across container targets, processor models, dialect selections, optimization toggles, and warning controls.

0.8.6 — 2026-10-08

Structured DSP parameters and diagnostics in machine-readable JSON reports, paired CLI options, and schema validation alignment.

New features

• Structured DSP reporting in JSON mode: --json output now reports resolved DSP target output kinds (dsp:lod, dsp:p56, etc.) and active dialect (asm56000), echoes DSP command parameters (format, org_p, org_x, org_y, entry_symbol), classifies DSP artifacts as dsp, and routes DSP warnings and errors to structured diagnostics with source file and line locations while keeping stderr silent.
• Paired CLI flags: added explicit enable and disable pairs for optimisation, relocations, symbols, and code generation flags (--opt-reorder / --no-opt-reorder, --pic / --no-pic, --relax / --no-relax, --strip / --no-strip, --sym-locals / --no-sym-locals, and ColdFire --cf-* / --cf-no-*).

Bug fixes

• JSON schema validation alignment: added no_emit and optional DSP fields to the documented schema definition, ensuring machine-readable output conforms to schema validation.

0.8.5 — 2026-10-07

Deprecation of legacy DSP directives and verification across processor switching combinations.

Deprecations

• Legacy DSP block directive deprecation: dsp and enddsp directives now emit diagnostic deprecation warnings in favor of .56001 ... .68000 or pushcpu 56001 ... popcpu.

Improvements

• Multi-target directive verification: verified combinations of memory space origins across 3 memory spaces, CPU stack state restoration, and dialect compatibility across 3 dialects (RMAC, VASM, and MADMAC).

0.8.4 — 2026-10-07

Scoped origin isolation and persistent location counters across heterogeneous processor blocks.

New features

• Scoped multi-target origin isolation: host 68k ORG directives and coprocessor memory spaces remain strictly isolated so that coprocessor ORG directives set DSP space origins without modifying host section offsets or preceding host origins.
• Persistent DSP location counters: multi-block heterogeneous DSP assembly maintains persistent P:, X:, Y:, and L: location counters across blocks in the same file, resuming assembly at the previous block's counter when an explicit origin is omitted.
• Scoped origin state stacking: pushcpu and popcpu save and restore memory space origins on an internal stack, preventing nested target blocks from altering outer target layout upon returning.

0.8.3 — 2026-10-07

Stack-based processor state switching and extended multi-target syntax for heterogeneous 680x0 and DSP56001 assembly.

New features

• Processor state push and pop: added pushcpu and popcpu directives for scoped CPU state management, allowing temporary target switches to 68020, 68030, ColdFire, or DSP56001 and restoring the previous processor context with balanced stack unwinding.
• Numeric CPU switching: added support for direct numeric processor directives (.56001, .68000, .68030) and pushcpu 56001 alongside dsp ... enddsp blocks in multi-target assembly.

0.8.2 — 2026-10-05

Fine-grained alignment control for inline DSP microkernels, supporting continuous multi-segment binary generation.

Improvements

• Heterogeneous DSP alignment suppression: added the noeven option to heterogeneous dsp directives (e.g. dsp packed, noeven), allowing suppression of automatic 68k word alignment when emitting contiguous multi-segment DSP streams.

0.8.1 — 2026-10-05

Hermetic execution and architectural isolation across 68000 and DSP assembly pipelines, enabling repeatable in-memory builds and test isolation.

Reliability

• Hermetic pipeline execution: assembly, equated symbol files, macro definitions, listings, and diagnostics run through isolated filesystem and environment ports, ensuring tests and tool invocations avoid global host interference.

0.8.0 — 2026-10-05

Multi-target support for Motorola DSP56001 assembly alongside 680x0. Adds standalone DSP assembly, binary and object output formats, in-file heterogeneous assembly (dsp ... enddsp) for inline Falcon DSP kernels, and bidirectional symbol and structure sharing between 68030 host and DSP code.

New features

• Standalone DSP56001 assembly: added --cpu=56001 (with dsp, dsp56k, and 56k aliases) and automatic source detection for .s56, .p56, and .asm56 files.
• DSP output formats: added support for 9 DSP output formats via --format: Motorola ASCII text (lod), a56 ASCII (out), Brainstorm multi-segment binary (p56), raw flat binary (bin), structured binary (dsp), Motorola COFF Load/Absolute (cld), Motorola COFF Relocatable (cln), and embeddable C (c/h) and ASM (inc/s) tables.
• In-file heterogeneous assembly: embedded dsp ... enddsp blocks in 680x0 sources assemble inline DSP routines directly into 68k sections with configurable wire formats (packed 3-byte words, unpacked 4-byte words, or bootstrap header) and automatic even alignment.
• Cross-architecture symbol and structure sharing: host 68k EQU/SET constants and macros are inherited in DSP blocks, and DSP labels are exported to 68k equates. Added word-addressed RSRESET/RS directives and dsp_import_struct scaling for 68k data structures.

0.7.20 — 2026-10-03

Support for numeric local labels in Motorola syntax assembly, and clean handling of reusable local label references.

New features

• Numeric local labels: numeric labels (1:, 2:) and backward/forward references (1b, 1f) are now supported across Motorola syntax assembly sources, matching compiler-generated inline assembly conventions.

0.7.19 — 2026-10-03

Addresses written as the sum of two names that are both defined further down the file now take the compact program-counter-relative form instead of failing the assembler's own layout check.

Bug fixes

• Addresses written as a sum of two later-defined names take the compact form: an address like a structure offset plus a data label, with both names defined further down, stayed in its widest absolute form while the final emit folded it to the shorter program-counter-relative form — the sizing model and the shipped bytes disagreed and the build was refused. Such sums now size against the compact form, verified in the assembler's relaxation test suite, while sums involving imports or undefined names keep the wide form.

0.7.18 — 2026-10-03

Data blocks sized by a variable that is given a new value further down the file now keep the size they were assembled with instead of failing the assembler's own layout check.

Bug fixes

• Data blocks sized by a counter that is reassigned later keep their assembled size: a data block whose size names a variable that changes value further down — a macro stamping filler words from a scratch counter, for example — was re-measured at the end of the file, shrinking it after the layout was fixed, and the build was refused. Such blocks now keep the size they were assembled with, verified in the assembler's relaxation test suite.

0.7.17 — 2026-10-03

A zero displacement written as a product with zero is now a constant in both sizing passes, so sources using that shape build instead of failing the assembler's own layout check.

Bug fixes

• A zero displacement spelled as a product with zero folds in both passes: a displacement like stride*0 stayed unresolved through the first sizing pass when the stride was not defined yet, so the compact form it folds to was never recorded — the final emit shed a word the layout was sized against and the build was refused. Such products now fold to zero in both passes, verified in the assembler's relaxation test suite.

0.7.16 — 2026-10-03

Two more silent mis-sizing classes closed in the layout engine: imported names that the same file goes on to define now fold to their compact form like any forward label, and data reservations whose length is computed from other symbols can no longer scramble a neighbouring reservation. Sources with these two shapes that previously failed the assembler's own layout check now build.

Bug fixes

• Imported names defined later in the same file fold to the compact form: a name brought in as an import but then defined in the same source stayed in its widest addressing form while the final emit folded it — the sizing model and the shipped bytes disagreed and the build was refused. Such names now size against their definition the way a forward label does in the assembler's relaxation test suite, while names that stay imported keep the wide form.
• Computed data reservations no longer overwrite their neighbours: a reservation whose length is computed from symbols (and comes out as zero on the first pass) records no layout of its own, so the size update meant for it could land on an unrelated reservation sharing the same address and erase it. Size updates now find their own reservation or do nothing.

0.7.15 — 2026-10-01

Branches to numeric local labels and FPU branch instructions now size and place correctly — three silent mis-assembly classes closed, and the layout self-checks now cover the positions those classes escaped through. Branch sizing now also accounts for the padding that org/rorg and alignment directives insert, so a branch whose span crosses one of those pads sizes against the layout the bytes actually ship at.

Bug fixes

• Numeric local labels track the relaxed layout: a label like 1: at the end of a region kept its pre-relaxation address, so a branch to it (bra 1f) could be emitted two bytes short of its target with no error reported. Numeric labels now move with the layout, and the final layout check compares them too — the drift that used to ship silently is a build failure.
• Forward branches to numeric labels relax: bra.s 1f and friends now size against the completed numeric-label list like any named target.
• FPU branches join branch relaxation: the word/long choice for FBcc was outside the sizing model entirely, so a lengthened span could disagree with the final layout — silently when the target was a numeric label at a region boundary. Both forms verified byte-identical against the reference assembler (vasm 2.0e) on the branch-sizing fixtures.
• Branches spanning org/rorg padding size against the real gap: a branch crossing one or more origin pads could be emitted two bytes short — or sized longer than needed — because the padding was invisible to the sizing model. Every padding form now participates in branch sizing, verified byte-identical against the reference assembler (vasm 2.0e) on the new padding fixtures, including the minimal landing across a pad.
• Branches spanning alignment padding size against the real pad: a cnop/alignment directive between a branch and its target is now measured the same way the final layout measures it, including when the pad itself grows as branch sizes settle. A grown alignment span that used to land two bytes off is verified byte-identical against the reference assembler (vasm 2.0e) on the alignment fixtures, and a span the reference assembler over-sizes converges to the true minimum.
• A section following an initial org keeps its symbols aligned with its bytes: content placed before the first org used to be counted twice between the symbol table and the emitted output, so the two disagreed about where later labels lived. The two now agree, verified byte-identical against the reference assembler.
• Empty macros contribute zero bytes to the layout: an empty macro invocation could record phantom length, shifting everything sized after it.
• Equates over a span track the relaxed layout: size equ end-start — the standard way to measure a span of code — kept its pre-relaxation value when the span grew, and the final layout check refused the build. Differences of two labels (or of the location counter and a label) now re-derive at the relaxed layout, verified byte-identical against the reference assembler (vasm 2.0e) on the equate fixtures.
• Branches to fixed addresses relax when growth demands it: a branch to a literal address (bra $40) kept the size recorded at its first measurement; growth before it could push the address out of that form's range with nothing re-checking. Such branches now re-size against the completed layout, verified byte-identical against the reference assembler (vasm 2.0e) on the literal-target fixture.
• Backward references re-shrink when the layout allows: a jmp/jsr or indexed operand measured against an early, inflated layout could be locked into its largest form even after the layout settled smaller. These now settle at the smallest form the final layout justifies — a far jump table indexed (d8,PC,Xn) recovers its compact form, verified byte-identical against the reference assembler (vasm 2.0e) on the indexed fixture.
• An undefined PC-indexed target holds the form the linker can patch: an unresolved move.w label(pc,d0.w),d0 reserved the widest indexed form during sizing, but the final emit has no wider PC-relative field a relocation can write — the two disagreed and the layout check refused the build. The sizing model now holds the brief form the relocation path ships.
• A branch to a literal address settles at the smallest form the final layout allows: a forward bra $100 behind items that grow kept the size of its first measurement even after that growth narrowed the distance into the short form's range, so the sizing model and the final emit disagreed and the build was refused. Literal targets now settle at the least size the finished layout justifies.
• A macro call between a call and its target no longer mis-pins the branch: a colon-free macro invocation (.mymac) expands to real bytes at encode time, but the branch-to-next check could not see it and pinned a jsr to its word form while the sizing model correctly chose the short one — the build was refused. The check now treats a macro call as the code it expands to.
• A branch whose target sits across rorg padding in a later section span stays minimal: when branch growth before the padding moved the branch closer to a target pinned by the rorg, the sizing engine measured the stale, pre-compensation distance and chose a larger form than the shipped layout needs — and the layout check refused the build. The padding compensation now applies across section spans as it does within one, verified on the relaxation test suite's padding fixtures.

Reliability

• The final layout check now covers section sizes as well as every label: a section that comes out a different length than the layout the branches were sized against fails the build instead of shipping.
• Padding participates in the layout self-checks: origin and alignment pads are derived from the same layout the checks prove minimal, so a pad that disagrees with the shipped layout is a build failure rather than a silent shift.
• Branch sizing grows to the correct form in one pass: an internal sizing step could stop one form short of the required one for far backward references, turning a valid program into a build refusal; the step now walks to the fitting form directly, verified on the production executables used for testing.
• The sizing cross-check now generates programs spanning the full directive set: the randomized layout harness covers numeric labels, literal targets, FPU branches, PC-indexed operands, alignment and origin padding, section round trips, equates and macro calls across two CPU generations and both output formats, and requires two independent sizing engines to agree on every generated program — the four fixes above are its finds.

0.7.14 — 2026-09-30

Branch sizing now happens in one pass over a recorded layout, with the assembler's own layout invariants executed as build-time checks — output verified byte-identical across the assembly corpus.

Reliability

• Layout post-conditions are executed: after the final encode, every emitted branch displacement is read back and checked against the size it shipped at, and the shipped layout is proven locally minimal — an internal sizing inconsistency is now a build failure instead of a silently widened field.
• Branch relaxation cannot refuse on default settings: the round limit is derived from the input itself (a converging layout cannot exceed it); an explicit round cap remains available and reports itself when exhausted.
• Forward-referenced equates resolve: an equate whose expression reads symbols defined later in the source (including across includes) is resolved after the first pass instead of being silently skipped.

Fidelity

• Label-minus-constant and label-plus-constant absolute operands (pointing at the word before a handler, or just past one) size identically to their bare-label spellings.
• Equates that read the location counter (label EQU *-4) and label differences in immediates (#table-base) track the final layout the way the previous multi-pass loop did — verified byte-identical on the assembly corpus.
• Structure-offset addressing with a zero offset (field(a5) where the field offset is zero) and far PC-relative indexed operands on 68020+ targets size from the completed symbol table.
• Branches across a section switch reserve the form the linker needs, and jump-to-next-instruction keeps its fall-through spelling while call-to-next keeps the word form a real call requires.

Performance

• Single-pass sizing: the front end runs once; relaxation is arithmetic over a recorded layout, with span positions in logarithmic time and rounds that visit only what grew — measured at roughly one visit per growth on a 220k-line cascade.
• The round limit is structural: derived from the input's own sizing range, so raising it is never needed for a converging source.

0.7.13 — 2026-09-26

Fixes mis-assemblies of register aliases in addressing modes, branches to keyword-named symbols, and nondeterministic object output.

Bug fixes

• Register aliases in pre-decrement and post-increment addressing: Register equates used as address registers (input EQUR a3, then move.b -(input),d6) resolve to the aliased register instead of reading as negative-displacement expressions.
• Branch instructions targeting keyword-named symbols: Branch instructions with offsets targeting symbols named after directives (bsr set+4, bra equ+8) assemble as branches rather than being parsed as equate definitions.
• Deterministic object output: Symbol table ordering in DRI and Pure C object file generation is now deterministic across build runs.

0.7.12 — 2026-09-23

Strict literal MOVEM preservation under non-optimizing mode.

Improvements

• Strict literal MOVEM assembly: Gated the single-register MOVEM -> MOVE peephole optimization behind its own size-optimization switch (active by default in the standard optimization profiles). Under --no-opt-size (-O0), explicit MOVEM.L <ea>,Rn instructions assemble verbatim as 0x4CDx without automatic folding to MOVE.L, enabling exact round-trip fidelity for disassembled source code.

0.7.11 — 2026-09-23

Fixes the glued Devpac define flag so the name keeps the case you typed.

Bug fixes

• Glued Devpac defines keep their spelling: -eFOO=7 now defines FOO, matching the separated -e FOO=7 form. Previously the glued form lower-cased the name to foo, so the two spellings of the same flag disagreed.

0.7.10 — 2026-09-20

Fixes memory indirect addressing parsing when PC is used as base with an index register.

Bug fixes

• Memory indirect PC-base addressing: Correctly parses ([0,PC,An]) and related memory indirect forms with PC base and an index register.

0.7.9 — 2026-09-20

Allows PC-relative destination operands on CMPI and clarifies the TST address register diagnostic.

Bug fixes

• CMPI with PC-relative destinations: Emits no warning on legal CMPI instructions reading PC-relative memory destinations (e.g. cmpi.b #$10,-4(PC)).
• TST address register diagnostic: Clarified that only byte size (TST.B An) is unencodable, while word and long sizes are supported on 68020+.

0.7.8 — 2026-09-17

Expands branch relaxation pass budget for large files and improves diagnostic messaging.

Bug fixes

• Branch relaxation budget: Increased default pass limit so large listings assemble without requiring --opt-relax-passes.
• Relaxation diagnostic: Clearly reports pass limits and the --opt-relax-passes=<N> override flag upon exhaustion.
• Zero-pass relaxation refusal: Refuses --opt-relax-passes=0 with a diagnostic rather than emitting unverified layouts.

0.7.7 — 2026-09-17

Refines TST address register checks against the declared target CPU architecture.

Bug fixes

• CPU-aware TST validation: Silences 68000-only warnings when assembling for 68020+ targets with .cpu 68020.

0.7.6 — 2026-09-13

Rejects shift and rotate counts that have no immediate encoding instead of silently assembling the wrong bytes.

Bug fixes

• Shift and rotate immediate bounds: Immediate counts outside 1..8 are rejected with an error rather than silently truncated to 3 bits.

0.7.5 — 2026-09-12

Added --summary flag (summary tables now off by default), display control flags (--color, --ascii, --banner), and graceful broken pipe handling on stdout.

Features

• Summary tables off by default (--summary): the section size and cycle total tables are now omitted unless --summary is passed on interactive stderr; --functions also enables the per-function breakdown.
• Display control flags: --color <auto|always|never> (honours NO_COLOR), --ascii for plain ASCII table borders, and --banner <logo|line|none> for masthead selection. --color=always keeps ANSI colour and boxed listings when piped into a pager such as less -R.

Bug fixes

• Broken stdout pipe: exits 0 instead of panicking when stdout is piped into head or less.

0.7.4 — 2026-09-09

Added .prgflags directive support for TOS executables.

Features

• PRG flags directive (.prgflags): Added .prgflags <expr> directive support, allowing source assembly to set the PRG flags in the generated .prg / .tos header.

0.7.3 — 2026-08-26

Test-infrastructure only: the shipped assembler is unchanged.

Improvements

• The test suite's scratch directories now remove themselves; the helper behind 44 tests never deleted them, leaving 177,488 on the build host.
• No assembler behaviour is affected — the change is confined to the test suite.

0.7.2 — 2026-08-25

Minor test suite hardening for deterministic non-terminal resolution.

Improvements

• Summary display precedence tests now resolve terminal capabilities explicitly.

0.7.1 — 2026-08-21

More floating-point coverage, a size-optimisation fix, and linker fixes for cases that could previously assemble or link to the wrong bytes. Default dialect output is unchanged.

New features

• FScc, FDBcc, and FTRAPcc now recognise and encode all 32 condition predicates, completing the FPU condition-code surface.
• Added a library option so callers that re-assemble their own listings can control instruction alignment independently of the selected dialect.
• Raw #{$w0,$w1,$w2} FPU immediates now also accept the 12-byte packed (.p) form, matching the packed listings produced for round-trip verification.

Bug fixes

• Invalid raw #{$...} floating-point immediates are now rejected instead of being silently dropped; previously the bytes after the instruction could be misaligned.
• --no-opt-size now keeps CMPA.L #n,An long as written; it was the one size transform that still fired with size optimisation disabled.
• Same-section PC-relative references are now recomputed by the linker when --relax is used, fixing cases where a function could resolve to a point inside itself.
• Expressions used as displacements now relocate correctly instead of turning into zero when they involve a symbol difference.
• A BSS section that references an external symbol now produces an error instead of silently dropping the reference.
• An unknown named section type is now reported as an error instead of being assembled into the current section.
• Named typed sections now keep their name where the output format supports it, so small-data sections can be placed by name.

Known issues

• With size optimisation enabled, an explicitly sized absolute address such as move.l ($52).l,d0 can still be shortened to word form; the explicit long form is currently treated as a size hint rather than a directive.

0.7.0 — 2026-07-29

Adds GenPC dialect support — Ziggy/OVR's PC cross-assembler (Overlanders). Use --dialect=genpc for GenPC and as68 sources.

New features

• --dialect=genpc: brace {/} macros, IF/WHILE/REPEAT, @ octal, Devpac-style text/end.
• Flat binary output with --raw; optional --reloc reloc-table trailer and --strip-bss tail trim.
• LS / LST symbol-file load; .SY2 overlay values when assembling with --reloc.

Improvements

• Default --dialect restored to vasm for Motorola-syntax sources.

Bug fixes

• GenPC: SY2 overlay reloc values, WHILE/REPEAT parse depth, and sizing defaults (forward branches word-sized, unsized MOVE defaults to word).

0.6.0 — 2026-07-27

Much broader dialect coverage and byte-level checks against classic Atari assemblers. Devpac, TurboAss, MADMAC, Alcyon and several other tools now have committed goldens; --strict-dialect catches foreign syntax more reliably.

New features

• Full-syntax corpora for TurboAss and DevpacST 1.01 (STANDARD / GenST TOS programs).
• Expanded MADMAC, Alcyon AS68, Lattice, SEKA, GST-ASM and other dialect packs with host oracles.
• Dialects and smoke harnesses for additional vendored assemblers (Sozobon, Josy, Brainstorm, MWC, AssemPro, GFA).
• LLVM-flavoured GAS ingestion path and a gas-llvm corpus.
• Aztec C Mot ingestion with a self-golden DRI pin (native ST AS.TTP still not available).

Improvements

• GenST / TurboAss --prg output matches classic empty-DATA and reloc trailers more closely.
• --strict-dialect promotes foreign-syntax heuristics to hard errors across dialects.
• Rejection checklists and negatives across all 22 dialect coverage matrices.

Bug fixes

• Fixed empty-DATA padding when text length was 2 mod 4 (vlink-style pad) for GenST-family and TurboAss programs.
• GenST 1.01 treats | as a line comment; ENDC handling matches the era.

0.5.6 — 2026-07-24

Added more vasm Mot and Pure C dialect coverage, and fixed a macro expansion crash. Building the macOS release no longer needs CoreFoundation.

New features

• Broader vasm Mot syntax: nested \@! / \@@ stacks, -allmp for args 10–35, include / offset / section, data aliases and conditionals.
• Pure C MACRO name.size sized-macro expansion, plus SET / EQU / MACRO / REPT / CPU coverage.
• Pure C object names and FIX tables closer to PASM.

Bug fixes

• Macro .size and \?0 expansion no longer panics.
• Dropped the chrono dependency so macOS cross-builds do not need CoreFoundation.

0.5.5 — 2026-07-22

Added support for additional dialects and improved the size optimiser. rg-asm now understands far more of RMAC's syntax, produces tighter code at the higher optimisation levels, and lays out Devpac-style object files more faithfully.

New features

• Much broader support for RMAC-style source, including its higher optimisation levels.
• Tighter code from the size optimiser: some absolute memory accesses become shorter PC-relative forms.
• Improved Devpac-compatible object output and listing formatting.

Bug fixes

• Fixed a false error on some forward references in indexed PC-relative addressing.
• More accurate instruction timing for immediate-to-register arithmetic.
• Corrected a few object-file layout details for better interoperability with other tools.

0.5.1 — 2026-07-20

Added a machine-readable JSON mode and an optional per-function size/timing table. Also fixed a pile of linker bugs — cases that used to emit subtly wrong programs now either work correctly or stop with a clear error.

New features

• A --json mode that prints one structured document you can feed to other tools.
• An optional --functions table showing the size and cycle cost of each function.

Bug fixes

• Fixed several linking bugs that could silently produce incorrect programs.
• Out-of-range jumps, bad relocations, and malformed flat images now stop with a clear error instead of emitting wrong bytes.

Breaking changes

• With no -o, the output file is now named after the input (main.s → main.prg) instead of always out.tos. Pass -o out.tos to keep the old name.
• The --summary options were replaced by --functions (the per-function table), -q (quiet), and --json (machine-readable).
• A few command-line flags were renamed for consistency; see the manual for the current names.
• The separate manual and man page were folded into the README that ships with the download.

0.1.0 — 2026-06-01

First public release. One self-contained assembler and linker for Atari ST and Falcon development — runs natively on Linux, macOS and Windows with nothing else to install. Free and open source (MIT or Apache-2.0).

New features

• Assembles Motorola syntax plus seven other classic assembler dialects, detected automatically per file.
• Links directly to ready-to-run Atari .TOS / .PRG programs.
• Supports the full 680x0 line (68000–68060) and ColdFire instruction sets, floating-point targets, and a size optimiser.
• Reads and writes six common Atari object-file formats (DRI, GST, Pure C, SEKA, a.out, and ELF), so it mixes cleanly with other toolchains.

Known issues

• A handful of 68030 memory-management instructions are recognised but not yet assembled; rg-asm reports an error for them rather than risk emitting wrong code.